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rt6908 ? ds6908-01 march 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? 1 pin configurations (top view) wqfn-40l 5x5 ordering information note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. general description the rt6908 provides a complete set of programmable multi-functional power solution for tft lcd panel. the rt6908 contains a step-up converter for main power and step-down controllers to provide the logic voltages for the system. moreover, a positive charge pump regulator provides the adjustable gate-high voltage, v gh ; a negative charge pump regulator provides the gate-low voltage, v gl . avdd, v gh and v gl outputs and power sequence can be programmable through i 2 c interface. with its high current capabilities, the device is ideal for large screen monitor panels and lcd tv applications with 12v supply voltage. the rt6908 is available in a wqfn- 40l 5x5 package. pmic for tft lcd tv panels applications z tft lcd tv panel features z z z z z 9v to 16v input supply voltage z z z z z 4.4a boost regulator for avdd with 12.7v to 19v programmable output z z z z z 1-ch sync. buck converter for v i/o z z z z z 1-ch sync. buck controller for v core z z z z z negative charge pump regulator for vgl with ? ? ? ? ? 8.1v to ? ? ? ? ? 1.8v programmable output z z z z z positive charge pump regulator for vgh with 24.5v to 40v programmable output z z z z z programmable sequencing z z z z z voltage detection output z z z z z over temperature protection z z z z z i 2 c compatible interface for register control z z z z z thin 40-lead wqfn package z z z z z rohs compliant and halogen free rt6908 package type qw : wqfn-40l 5x5 (w-type) lead plating system z : eco (ecological element with halogen free and pb free) marking information pgnd rstb comp1 lxi gd avdd vdet sda scl fbb1 boot2 nc dhb2 drvn crst comp2 fbb2 dlb2 ilimit2 lxb2 comp a0 pgnd lx lx lx pgnd vgl vgh drvp lxb1 lxb1 boot1 nc vinb1 avin agnd vl en en_i2c 1 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 31 32 33 34 35 36 37 38 39 40 41 pgnd RT6908ZQW : product number ymdnn : date code rt6908 zqw ymdnn
rt6908 2 ds6908-01 march 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? typical application circuit rt6908 lx lxi avin 14, 15, 16 10 120f 6.8h 1f vl boot1 35 33 38 36 vinb1 1f 0.1f 10f 22f v in 12v 39, 40 lxb1 10h fbb1 2 v i/o 3.3v a0 12 rstb 4 avdd 100k 47nf 0.22f 6.8 35.5v v gh drvp vgh lxb1 20 19 agnd 34 1, 13, 17, 41 (exposed pad) pgnd 2.2nf 4.7nf gd avdd 10f 8 9 22f x 2 100pf 47k 15k 0.1f 6.8 0.22f 6.8 lx 6.8 10f avdd 15.6v sda v i/o scl scl sda 4.7k 4.7k 4.7k rstb 5 6 100k drvn 21 0.22f 6.8 lxb1 6.8 47nf -6v v gl 10f vgl 18 22 crst 22nf v core 1.1v 10f 4.7h v in 0.22f 1nf 1.5 30 boot2 28 dhb2 26 dlb2 29 lxb2 10k 24k 10pf 1nf 24k 24 fbb2 23 comp2 1.2k 470pf 22f x 3 20k en 32 vl en_i2c 31 vl vdet 7 v i/o 47k 15k 470pf 3 comp1 120k 25 ilimit2 33k c1 l1 c6 c7 c8 l2 c11 r2 r3 c12 c13 r4 c19 r5 r6 r27 r10 m1 c20 c21 m2 c22 r13 l3 r11 c23 r14 c24 r12 r23 c25 c26 r24 r25 r26 d1 c2 q1 c3 c4 c5 r1 c9 1f q2 c10 c14 r7 r8 c15 d2 d3 d4 d5 c16 r9 r10 c17 c18 r16 r17 r18 c27 r19 q3 d6 d7 c28 r20 r21 c29 11 220k 330pf comp r22 c30
rt6908 3 ds6908-01 march 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? timing diagram figure 2. default mode power sequence (v en_i2c = 0) figure 1. i 2 c mode power sequence (v en_i2c = 1) control byte (internal register) v en_i2c avdd 300s v core 1.1v vgh v rstb 3ms t crst vgl 4ms t dly3 300s v i/o 3.3v vdet i 2 c bus t dly1 t dly2 tcon program t ss 0xff=0x55 dly1,dly2 begins start up 12v or vl v en 12v or vl t cgd q1 vsg (v lxi - v gd ) 4v v en_i2c avdd 300s v core 1.1v vgh v rstb 3ms t crst vgl 300s v i/o 3.3v vdet i 2 c bus t dly1 0v v en 12v or vl (default voltage : -6v) (default : 200ms) (default : 10ms) (default : 2ms) (default : 400ms) (default voltage : 15.6v) 4ms t dly3 t ss t cgd (default voltage : 35.5v) t dly2 q1 vsg (v lxi - v gd ) 4v
rt6908 4 ds6908-01 march 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? functional pin description pin no. pin name pin function 1, 13, 17, 41(exposed pad) pgnd power ground. the exposed pad must be soldered to a large pcb and connected to pgnd for maximum thermal dissipation. 2 fbb1 feedback input for buck1 converter. 3 comp1 compensation pin for buck1 converter. this pin is the output node of the error amplifier. 4 rstb voltage detector open-drain output. 5 sda i 2 c compatible serial data input/output. 6 scl i 2 c compatible serial clock input. 7 vdet voltage detector input. 8 avdd output sense pin for boost converter avdd. 9 gd gate drive. used to control an external mosfet switch to provide input to output isolation of avdd. 10 lxi isolation switch input. 11 comp boost converter (avdd) compensation. connect a compensation network to ground. 12 a0 i 2 c compatible device address bit 0. 14, 15, 16 lx boost converter (avdd) switch. connect an inductor between this pin and input voltage source. 18 vgl output sensing pin of vgl negative charge pump. 19 vgh output sensing pin of vgh positive charge pump. 20 drvp base drive of external pnp transistor for vgh positive charge pump. 21 drvn base drive of external npn transistor for vgl negative charge pump. 22 crst voltage detector delay capacitor connection. connect capacitor from this pin to ground. 23 comp2 compensation pin for buck2 converter. 24 fbb2 feedback input for buck2 converter. 25 ilimit2 current limit adjustment for buck2 converter. connect a resistor from ilimit2 to agnd to adjust the current limit threshold below 300mv. 26 dlb2 low side gate driver output for buck2 converter. 27, 37 nc not internal connected. should be floating or connected to gnd figure 3. i 2 c interface timing diagram sda scl t hd, sta t su, dat t hd, dat t su, sta t hd, sta t sp t buf t low t high t su, sto t r t f start condition repeated start condition stop condition start condition
rt6908 5 ds6908-01 march 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? pin no. pin name pin function 28 dhb 2 high side gate driver output for buck2 converter. 29 lxb 2 buck2 converter switch node between high side mosfet and low side mosfet. 30 boot2 n-mosfet gate drive voltage for buck2 converter. connect a capacitor from the switch node lxb2 to this pin. 31 en_i2c enable for i 2 c control. avdd, vgl, vgh enabled by i 2 c control. 32 en chip enable (active high). tie to vl to enable the device. 33 vl internal logic regulator output. connect this pin with a decoupling capacitor. 34 agnd analog ground. 35 av in analog input voltage of the device. this is the input for the analog circuits. connect this pin with a decoupling capacitor. 36 vin b1 power input voltage pins for the v i/o buck converter. 38 boot1 n-mosfet gate drive voltage for buck1. connect a capacitor from the switch node lxb1 to this pin. 39 lxb1 buck1 switch node between high side mosfet and low side mosfet. 40 lxb1 buck1 switch node between high side mosfet and low side mosfet. function block diagram internal regulator sync. buck1 avin vl boot1 vinb1 lxb1 fbb1 boost lxi gd avdd comp lx sequence control en_i2c dc/dc dac reg i 2 c interface sda scl a0 vdet vgl regulator vl drvn vgh regulator drvp vgh dhb2 pgnd agnd voltage detector en rstb crst sync. buck2 lxb2 dlb2 fbb2 comp2 ilimit2 boot2 vl vgl comp1
rt6908 6 ds6908-01 march 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? (typical values v in = v avin = v inb = 12v, v avdd = 15.6v, v i/o = 3.3v, v core = 1.1v, v gh = 35.5v, v gl = ? 6v, t a = 25 c, unless otherwise specified) electrical characteristics recommended operating conditions (note 4) z junction temperature range -------------------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range -------------------------------------------------------------------------------------------- ? 40 c to 85 c parameter symbol test conditions min typ max unit supply current input voltage range v in 9 -- 16 v avin quiescent current i qin lx, lxbx not switching -- 3.5 -- ma v in rising -- 8.6 9 v in falling 7.2 7.6 -- under voltage lockout threshold v uvlo v in falling latch reset -- 5 -- v vl output voltage v l -- 5 -- v fault detection fault trigger duration -- 50 -- ms thermal shutdown threshold temperature rising -- 150 -- c thermal shutdown hysteresis -- 50 -- c absolute maximum ratings (note 1) z en, en_i2c, avin, vinb1, lxi, gd, avdd, lx, lxb1, lxb2, boot1, boot2, dhb2, vdet to pgnd ----------------------------------------------------------------------------- ? 0.3 to 26v z sda, scl, a0, rstb, crst, vl, comp, comp1, comp2, fbb1, fbb2, ilimit2, dlb2, drv n to pgnd -------------------------------------------------------------------------------- ? 0.3 to 6v z boot1 to lxb1 ------------------------------------------------------------------------------------------------------------- ? 0.3 to 6v z boot2, dhb2 to lxb2 --------------------------------------------------------------------------------------------------- ? 0.3 to 6v z drvp, v gh to pgnd ----------------------------------------------------------------------------------------------------- ? 0.3 to 44v z vgl to pgnd --------------------------------------------------------------------------------------------------------------- ? 26v to 26v z pgnd to agnd ------------------------------------------------------------------------------------------------------------- 0.3v z power dissipation, p d @ t a = 25 c wqfn-40l 5x5 ------------------------------------------------------------------------------------------------------------- 2.778w z package thermal resistance (note 2) wqfn-40l 5x5, ja -------------------------------------------------------------------------------------------------------- 36 c/w wqfn-40l 5x5, jc ------------------------------------------------------------------------------------------------------- 6 c/w z lead temperature (soldering, 10 sec.) -------------------------------------------------------------------------------- 260 c z junction temperature ------------------------------------------------------------------------------------------------------ 150 c z storage temperature range --------------------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body model) ----------------------------------------------------------------------------------------------- 2kv mm (ma chine model) ------------------------------------------------------------------------------------------------------ 200v
rt6908 7 ds6908-01 march 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? parameter symbol test conditions min typ max unit logic inputs (sda, scl, en, en_i2c) input high voltage v ih 1.7 -- -- v input low voltage v il -- -- 0.6 v input leakage current i ih , i il v in = 0 or 3.3v ? 1 0.01 1 a input capacitance -- 5 -- pf sda output low voltage v ol i sink = 6ma -- 0.3 -- v i 2 c timing characteristics serial-clock frequency f scl 0 -- 400 khz bus free time between stop and start conditions t buf 1.3 -- -- s hold time (repeated) start condition t hd, sta 0.6 -- -- s scl pulse-width low t low 1.3 -- -- s scl pulse-width high t high 0.6 -- -- s setup time for a repeated start condition t su, sta 0.6 -- -- s data hold time t hd, dat 0 -- 800 ns data setup time t su, dat 100 -- -- ns sda and scl receiving rise time t r 20 + 0.1c b -- 300 ns sda and scl receiving fall time t f 20 + 0.1c b -- 300 ns sda transmitting fall time t f 20 + 0.1c b -- 250 ns setup time for stop condition t su, sto 0.6 -- -- s bus capacitance c b -- -- 400 pf pulse w idth of suppressed spike t sp -- -- 50 ns reset voltage detector minimum operating voltage avin minimum voltage for rstb 2.2 -- -- v vdet detecting threshold v th vdet falling -- 0.6 -- v vdet threshold hysteresis v th -- 100 -- mv rstb output low voltage v ol i sink = 500 a -- -- 0.3 v rstb leakage current i leak v rstb = 5.0v -- 0.01 0.1 a crst charge current i crst -- 8 -- a crst threshold v crst -- 1.25 -- v boost converter (avdd) adjustable output voltage range v avdd register address = ?00h?, 6 bits, avdd = (12.7v to 19v) [00h to 3fh] 12.7 -- 19 v avdd regulation voltage (default) v avdd no load 15.444 15.6 15.756 v oscillator frequency f osc 600 750 900 khz maximum duty cycle -- 90 -- %
rt6908 8 ds6908-01 march 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? parameter symbol test conditions min typ max unit n-mosfet on-resistance r ds(on) i lx = 500ma -- 120 -- m n-mosfet switch current limit i lim 4.4 5.6 -- a switch leakage current i leak v lx = 19v -- 1 10 a lxi over voltage protection v ovp v lx rising, hysteresis = 1v 19.5 20 -- v avdd line regulation 9v v in 16v, i out = 1ma -- 0.004 -- %/v avdd load regulation 1ma i out 2a -- 0.1 -- %/a trans-conductance of error amplifier gm -- 100 -- a/v avdd fault trip level v ft_avdd v avdd falling v avdd x 76% v avd d x 80% v avdd x 84% v isolation switch control gd pull down voltage v lxi ? v gd 5 6 7 v gd sink current i gd 8 12 16 a gd pull up resistance r gd 8 12 16 k short-circuit trigger duration i avddd ilimgd / r on, pmos -- 200 -- s buck1 controller (v i/o ) fbb1 regulation voltage v fbb1 no load 0.788 0.8 0.812 v oscillator frequency f osc 400 500 600 khz phase shift between buck1 and buck2 -- 180 -- -- maximum duty cycle -- 86 -- % trans-conductance of error amplifier gm -- 100 -- a/v lxb1 to vinb1 n-mosfet on-resistance r ds(on) i lxb1 = 500ma -- 200 -- m lxb1 to pgnd n-mosfet on-resistance i lxb1 = 500ma -- 150 -- m soft-start period t ss_i/o -- 300 -- s fbb1 fault trip level v fbb1 falling 0.6144 0.64 0.6656 v lxb1 positive current limit i lim 3 3.8 -- a buck2 controller (v core ) fbb2 regulation voltage v fbb2 no load 0.788 0.8 0.812 v oscillator frequency f osc 400 500 600 khz phase shift between buck1 and buck2 -- 180 -- -- maximum duty cycle -- 50 -- % boot2 to dhb2 p-mosfet on-resistance r ug(on)_dhb2 i lxb2 = 100ma -- 1.8 -- dhb2 to lxb2 n-mosfet on-resistance r lg(on)_dhb2 i lxb2 = 100ma -- 0.6 -- lxb2 to dlb2 p-mosfet on-resistance r ug(on)_dlb2 i lxb2 = 100ma -- 2 -- dlb2 to pgnd n-mosfet on-resistance r lg(on)_dlb2 i lxb2 = 100ma -- 0.5 -- soft-start period t ss_core -- 300 -- s
rt6908 9 ds6908-01 march 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? parameter symbol test conditions min typ max unit fbb2 fault trip level v fbb2 falling 0.6144 0.64 0.6656 v fbb2 short trip level v fbb2 falling -- 0.16 -- v ilimit2 source current -- 40 -- a low side switch current limit cycle by cycle -- v ilimit2 / 8 -- v maximum ilimit2 voltage setting -- 2.4 -- v negative charge pump controller (vgl) vgl adjustable output voltage range v gl register address = ?02h?, 6 bits, v gl = ( ? 1.8v to ? 8.1v) [00h to 3fh] ? 8.1 -- ? 1.8 v vgl regulation voltage (default) v gl v drvn = 0.6v, i drvn = ? 100 a ? 6.3 ? 6 ? 5.7 v drvn sink current limit i drvn,max v drvn = 0.6v -- 3.5 5 ma drvn short circuit current i drvn,sc v gl > ? 0.5v -- 300 -- a vgl load regulation error v drvn = 0.6v, ? 50 a < i drvn < ? 1ma -- 60 -- mv/ma soft-start period t ss -- 3 -- ms vgl fault trip level v gl rising v gl + 1.5 -- v gl + 2.5 v vgl short trip level v gl rising ? 0.5 v positive charge pump controller (vgh) vgh adjustable output voltage range v gh register address = ?01h?, 5 bits, v gh = (24.5v to 40v) [00h to 1fh] 24.5 -- 40 v vgh regulation voltage (default) v gh v drvp = 15.6v, i drvp = 100 a 34.79 35.5 36.21 v drvp source current limit i drvp,max v drvp = 15.6v -- 3.5 5 ma drvp short circuit current i drvp,sc v gh < 20% -- 80 -- a vgh load regulation error v drvp = 15.6v, 50 a < i drvp < 1ma -- 300 -- mv/ma soft-start period t ss -- 4 -- ms vgh fault trip level v gh falling v gh x 70 v gh x 75 v gh x 80 % vgh short trip level v gh falling -- 20 -- % note 1. stresses beyond those listed ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions may affect device reliability. note 2. ja is measured at t a = 25 c on a high effective thermal conductivity four-layer test board per jedec 51-7. jc is measured at the exposed pad of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions.
rt6908 10 ds6908-01 march 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? typical operating characteristics boost efficiency vs. load current 50 60 70 80 90 100 0 0.4 0.8 1.2 1.6 2 load current (a) efficiency (%) v in = 12v, v avdd = 15.6v buck1 efficiency vs. load current 50 60 70 80 90 100 0 0.4 0.8 1.2 1.6 2 load current (a) efficiency (%) v in = 12v, v i/o = 3.3v buck2 efficiency vs. load current 50 60 70 80 90 100 0 0.4 0.8 1.2 1.6 2 load current (a) efficiency (%) v in = 12v, v core = 1.1v buck1 output voltage vs. load current 2.4 2.7 3.0 3.3 3.6 3.9 00.511.52 load current (a) output voltage (v) v in = 12v, v i/o = 3.3v buck2 output voltage vs. load current 0.8 0.9 1.0 1.1 1.2 1.3 00.511.52 load current (a) output voltage (v) v in = 12v, v core = 1.1v boost output voltage vs. load current 14.0 14.5 15.0 15.5 16.0 16.5 17.0 00.511.52 load current (a) output voltage (v) v in = 12v, v avdd = 15.6v
rt6908 11 ds6908-01 march 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? buck2 output voltage vs. temperature 0.8 0.9 1.0 1.1 1.2 1.3 -50 -25 0 25 50 75 100 125 temperature (c) output voltage (v) v in = 12v, v core = 1.1v vgh output voltage vs. temperature 33 34 35 36 37 38 -50-25 0 25 50 75100125 temperature (c) output voltage (v) v in = 12v, v gh = 35.5v buck1 output voltage vs. temperature 3.0 3.1 3.2 3.3 3.4 3.5 -50-25 0 25 50 75100125 temperature (c) output voltage (v) v in = 12v, v i/o = 3.3v boost output voltage vs. temperature 14.0 14.5 15.0 15.5 16.0 16.5 17.0 -50 -25 0 25 50 75 100 125 temperature (c) output voltage (v) v in = 12v, v avdd = 15.6v vgh output voltage vs. load current 33 34 35 36 37 38 0 1530456075 load current (ma) output voltage (v) v in = 12v, v gh = 35.5v vgl output voltage vs. load current -8 -7 -6 -5 -4 -3 0 1530456075 load current (ma) output voltage (v) v in = 12v, v gl = ? 6v
rt6908 12 ds6908-01 march 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? time (500 s/div) boost load transient response v in = 12v, v avdd = 15.6v, r22 = 220k , c30 = 330pf, c31= 10pf v avdd _ac (500mv/div) i avdd (1a/div) time (100ms/div) v in = 12v, v avdd = 15.6v, v i/o = 35.5v, v gl = -6v, c17= 22nf power on sequence 2 v avdd (10v/div) v gh (20v/div) v gl (5v/div) v rstb (2v/div) time (500 s/div) buck1 load transient response v in = 12v, v i/o = 3.3v, r4 = 120k , c19 = 470nf v i/o _ac (100mv/div) i i/o (1a/div) time (500 s/div) buck2 load transient response v in = 12v, v core = 1.1v, r23 = 24k , c25 = 1nf, c26 = 10pf, r14 = 1.2k , c23 = 470pf v core _ac (100mv/div) i core (1a/div) vgl output voltage vs. temperature -8 -7 -6 -5 -4 -3 -50 -25 0 25 50 75 100 125 temperature (c) output voltage (v) v in = 12v, v gl = ? 6v time (1ms/div) power on sequence 1 v en (5v/div) v core (1v/div) v i/o (2v/div) v rstb (2v/div) v in = 12v, v core = 1.1v, v i/o = 3.3v, c17= 22nf
rt6908 13 ds6908-01 march 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? application information i 2 c command single i 2 c register write protocol single i 2 c register read protocol multiple i 2 c register write protocol multiple i 2 c register read protocol register map address name description default value resolution range 00h avdd [5 : 0] boost 15.6v (1dh) 0.1v 12.7v to 19v (00h to 3fh) 01h vgh [4 : 0] vgh 35.5v (16h) 0.5v 24.5v to 40v (00h to 1fh) 02h vgl [5 : 0] vgl ? 6v (2ah) ? 0.1v ? 1.8v to ? 8.1v (00h to 3fh) 03h vio [3 : 0] vio adjustment 0% (07h) 1% ? 7% to 7% (00h to 0eh) 04h v core [3 : 0] v core adjustment 0% (07h) 1% ? 7% to 7% (00h to 0eh) 05h dly1 [3 : 0] vgl delay time 200ms (01h) dlyr1 0 to 15 x dlyr1 (00h to 0fh) 06h dly2 [3 : 0] avdd delay time 400ms (02h) dlyr2 0 to 15 x dlyr2 (00h to 0fh) 07h dly3 [3 : 0] vgh delay time 10ms (01h) dlyr3 0 to 15 x dlyr3 (00h to 0fh) 08h dlyr1 [1 : 0] dly1 resolution 200ms (02h) 1ms, 10ms, 200ms 09h dlyr2 [1 : 0] dly2 resolution 200ms (02h) 1ms, 10ms, 200ms 0ah dlyr3 [1 : 0] dly3 resolution 10ms (01h) 1ms, 10ms, 200ms 0bh ss [3 : 0] avdd soft-start time 2ms (02h) 1ms 0ms to 15ms (00h to 0fh) 0ch ilimgd [3 : 0] isolation switch current limit disable (00h) 50mv disable, 100mv to 800mv (00h to 0fh) ffh ctrl [7 : 0] ??55h?? start power on sequence 00h slave address 1 1 0 1 0 0 0 register address d7 d6 d5 d4 d3 d2 d1 d0 slave ack stop slave ack slave ack a0 stop slave address 1 1 0 1 0 0 0 register address slave ack slave ack stop slave ack a0 master nack stop slave address re- start 1 1 0 1 0 0 1 a0 d7 d6 d5 d4 d3 d2 d1 d0 slave address 7 6 5 4 3 2 1 0 = lsb 1 1 0 1 0 0 a0 r/w slave address 1 1 0 1 0 0 0 register address d7 d6 d5 d4 d3 d2 d1 d0 slave ack slave ack slave ack a0 stop d7 d6 d5 d4 d3 d2 d1 d0 slave ack d7 d6 d5 d4 d3 d2 d1 d0 slave ack stop slave address 1 1 0 1 0 0 0 register address slave ack slave ack stop slave ack a0 master nack stop slave address re- start 1 1 0 1 0 0 1 a0 d7 d6 d5 d4 d3 d2 d1 d0 master ack d7 d6 d5 d4 d3 d2 d1 d0
rt6908 14 ds6908-01 march 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? output code table (unit : v) register code avd d vgh vgl v io v core dly1 dly2 dly3 dlyr1 dlyr2 dlyr3 ss ilimgd 00h 12.7 24.5 ? 1.8 ? 7% ? 7% 0ms 0ms 0ms 1ms 1ms 1ms 0ms disable 01h 12.8 25.0 ? 1.9 ? 6% ? 6% 1ms 1ms 1ms 10ms 10ms 10ms 1ms 100mv 02h 12.9 25.5 ? 2.0 ? 5% ? 5% 2ms 2ms 2ms 200ms 200ms 200ms 2ms 150mv 03h 13.0 26.0 ? 2.1 ? 4% ? 4% 3ms 3ms 3ms 3ms 200mv 04h 13.1 26.5 ? 2.2 ? 3% ? 3% 4ms 4ms 4ms 4ms 250mv 05h 13.2 27.0 ? 2.3 ? 2% ? 2% 5ms 5ms 5ms 5ms 300mv 06h 13.3 27.5 ? 2.4 ? 1% ? 1% 6ms 6ms 6ms 6ms 350mv 07h 13.4 28.0 ? 2.5 0 0 7ms 7ms 7ms 7ms 400mv 08h 13.5 28.5 ? 2.6 1% 1% 8ms 8ms 8ms 8ms 450mv 09h 13.6 29.0 ? 2.7 2% 2% 9ms 9ms 9ms 9ms 500mv 0ah 13.7 29.5 ? 2.8 3% 3% 10ms 10ms 10ms 10ms 550mv 0bh 13.8 30.0 ? 2.9 4% 4% 11ms 11ms 11ms 11ms 600mv 0ch 13.9 30.5 ? 3.0 5% 5% 12ms 12ms 12ms 12ms 650mv 0dh 14.0 31.0 ? 3.1 6% 6% 13ms 13ms 13ms 13ms 700mv 0eh 14.1 31.5 ? 3.2 7% 7% 14ms 14ms 14ms 14ms 750mv 0fh 14.2 32.0 ? 3.3 15ms 15ms 15ms 15ms 800mv 10h 14.3 32.5 ? 3.4 11h 14.4 33.0 ? 3.5 12h 14.5 33.5 ? 3.6 13h 14.6 34.0 ? 3.7 14h 14.7 34.5 ? 3.8 15h 14.8 35.0 ? 3.9 16h 14.9 35.5 ? 4.0 17h 15.0 36.0 ? 4.1 18h 15.1 36.5 ? 4.2 19h 15.2 37.0 ? 4.3 1ah 15.3 37.5 ? 4.4 1bh 15.4 38.0 ? 4.5 1ch 15.5 38.5 ? 4.6 1dh 15.6 39.0 ? 4.7 1eh 15.7 39.5 ? 4.8 1fh 15.8 40.0 ? 4.9 20h 15.9 ? 5.0 21h 16.0 ? 5.1 22h 16.1 ? 5.2 23h 16.2 ? 5.3 24h 16.3 ? 5.4 25h 16.4 ? 5.5
rt6908 15 ds6908-01 march 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? register code avdd vgh vgl vio v core dly1 dly2 dly3 dlyr1 dlyr2 dlyr3 ss ilimgd 26h 16.5 ? 5.6 27h 16.6 ? 5.7 28h 16.7 ? 5.8 29h 16.8 ? 5.9 2ah 16.9 ? 6.0 2bh 17.0 ? 6.1 2ch 17.1 ? 6.2 2dh 17.2 ? 6.3 2eh 17.3 ? 6.4 2fh 17.4 ? 6.5 30h 17.5 ? 6.6 31h 17.6 ? 6.7 32h 17.7 ? 6.8 33h 17.8 ? 6.9 34h 17.9 ? 7.0 35h 18.0 ? 7.1 36h 18.1 ? 7.2 37h 18.2 ? 7.3 38h 18.3 ? 7.4 39h 18.4 ? 7.5 3ah 18.5 ? 7.6 3bh 18.6 ? 7.7 3ch 18.7 ? 7.8 3dh 18.8 ? 7.9 3eh 18.9 ? 8.0 3fh 19.0 ? 8.1 40h if register data out of spec, ic will be into default value.
rt6908 16 ds6908-01 march 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? the rt6908 is a programmable multi-functional power solution for tft lcd panels. the rt6908 contains a step- up converter for main power, a synchronous buck converter and a synchronous buck controller to provide the logic voltages for timing controller, voltage detector for the system. moreover, a positive charge pump regulator provides the adjustable gate-high voltage and a negative charge pump regulator provides the gate low voltage. boost converter the boost converter is high efficiency pwm architecture. it performs fast transient responses to generate source driver supplies for tft lcd display. the high operation frequency allows use of smaller components to minimize the thickness of the lcd panel. the output voltage can be achieved by setting the i 2 c register 00h [5:0]. the boost minimum gain ratio depends on minimum on time. it suggested that avdd higher than 1.14xvin for better performance. boost soft-start the main boost converter has an internal soft-start function to reduce the input inrush current. the soft-start time can be achieved from 0ms to 15ms by setting the i 2 c register 0bh [3:0]. boost over voltage protection the main boost converter has an over voltage protection to protect the main switch at the lxi pin. when the lxi pin voltage rises above 20v, the boost converter turns the switch off. as soon as the output voltage falls below the over voltage threshold, the converter will resume operation. boost over current protection the rt6908 senses the inductor current that is flowing into the lx pin. the internal n-mosfet will be turned off if the peak inductor current reaches 5.6a (typ.). thus, the output current at the current limit boundary, denoted as i out(lim) , can be calculated according to the following equation : ? ?? ? ?? ?? in out in s in out(lim) lim out out v(v v) t v 1 i = i v2vl where is the efficiency of the boost converter, i lim is the value of the current limit and t s is the switching period. boost short circuit protection the main boost converter has a short circuit protection. this function disables the boost converter and isolation p-mosfet if the difference voltage between the lxi and avdd pin larger than ilimgd i 2 c register 0ch [3:0] setting. the ic will shut down if this difference voltage remains above setting value after 200 s. besides, ic will also shut down if input voltage below uvlo threshold at avdd short circuit period. only input voltage below 5v (typ.) then re- power on and remove fault condition, ic can return to normal operation. boost under voltage fault protection the main boost converter has a fault protection. this function disables the boost converter if avdd is detected to be below 80%. the ic will shut down if avdd remains below 80% after 50ms. boost inductor selection the inductor value depends on the maximum input current. as a general rule the inductor ripple current is 20% to 40% of maximum input current. if 40% is selected as an example, the inductor ripple current can be calculated according to the following equation : out out(max) in(max) in ripple in(max) vi i = v i = 0.4i where is the efficiency of the boost converter, i in(max) is the maximum input current and i ripple is the inductor ripple current. the input peak current can be obtained by adding the maximum input current with half of the inductor ripple current as shown in the following equation : i peak = i ripple + i in(max) = 1.2 i in(max) note that the saturated current of inductor must be greater than i peak . the inductance can eventually be determined according to the following equation : ()( ) () ? 2 in out in 2 out out(max) osc vvv l = 0.4 v i f where f osc is the switching frequency. for better system performance, a shielded inductor is preferred to avoid emi problems.
rt6908 17 ds6908-01 march 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? boost diode selection the schottky diode is a good choice for any asynchronous boost converter due to the small forward voltage. however, when selecting a schottky diode, important parameters such as power dissipation, reverse voltage rating, and pulsating peak current must all be taken into consideration. a suitable schottky diode's reverse voltage rating must be greater than the maximum output voltage, and its average current rating must exceed the average output current. boost input capacitor selection low esr ceramic capacitors are recommended for input capacitor applications. low esr will effectively reduce the input ripple voltage caused by the switching operation. another consideration is the voltage rating of the input capacitor, which must be greater than the maximum input voltage. boost output capacitor selection output ripple voltage is an important index for estimating the performance. a 120 f low esr os-cap is sufficient for most applications. this portion consists of two parts, one is the product of i in and esr of output capacitor, another part is formed by charging and discharging process of output capacitor. as shown in figure 4, v out1 can be evaluated based on the ideal energy equalization. according to the definition of q, the q value can be calculated as the following equation : ?? ??? ? ? ?? ??? ? ?? ??? ? ?? in l out in l out in out out1 out osc 11 1 q = i+ ii +i ii 22 2 v 1 =c v vf where f osc is the switching frequency and the i l is the inductor ripple current. move c out to the left side to estimate the value of v out1 as the followi ng equation : out out1 out osc di v = cf finally, the output ripple voltage can be determined as following equation : ? out out in out osc di v = iesr+ cf time time inductor current output current output ripple voltage (ac) (1-d)t s v out1 i l input current figure 4. the output ripple voltage without the contribution of esr boost loop compensation the voltage feedback loop can be compensated with an external compensation net work consisted of r22 and c30. choose r22 to set the high frequency integrator gain for fast transient response. and choose c30 to set the integrator zero to maintain stability. vi/o synchronous buck converter the buck converter is a high efficiency pwm architecture with 500khz operation frequency and fast transient response. the converter drives an internal n-mosfet, connected between the vinb1 and lxb1 pin. connect a 100nf low esr ceramic capacitor between the boot1 pin and lxb1 pin to provide gate driver voltage for the high side mosfet. vi/o buck output voltage setting the regulated default output voltage is as shown in the following equation : ?? ?? ?? i/o fbb1 fbb1 r2 v = v 1 + , where v = 0.8v (typ.) r3 the recommended value for r2 should be up to 10k without some sacrificing. to place the resistor divider as close as possible to the chip can reduce noise sensitivity. the output voltage also can be adjusted from ? 7% to 7% by setting the i 2 c register 03h [3:0].
rt6908 18 ds6908-01 march 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? vi/o buck soft-start the step-down converter has an internal soft-start to reduce the input inrush current. when the buck converter is enabled, the output voltage rises slowly from zero to the regulated voltage. the typical soft-start time is around 300 s. vi/o buck over current protection t he ic senses the inductor current that is flowing out the lxb1 pin. t he internal mosfet will be turned off if the peak inductor current reaches 3.8a (typ.). vi/o buck short circuit protection to limit the short circuit current, the device has a cycle- by-cycle current limit. to avoid the short circuit current from rising above the internal current limit when the output is shorted to gnd, the switching frequency is reduced as well. the switching frequency is reduced to one-half of original frequency when the output voltage is below 80% and to one-fourth of the original frequency when the output voltage is below 20%. if the ? short ? is r emoved, the buck converter will resume operation. if the voltage remains below 80% after 50ms, the ic will shut down. vi/o buck loop compensation the voltage feedback loop can be compensated with an external compensation network consisted of the r4 and c19. choose r4 to set high frequency integrator gain for fast transient response. and choose the c19 to set the integrator zero to maintain stability. vcore synchronous buck controller the synchronous buck controller is a high efficiency pwm architecture with 500khz operation frequency and fast transient response. the controller need external high side and low side n-mosfet as synchronous rectifier and does not required schottky diode on the lxb2 pin. the high side mosfet is connected between vin and the lxb2 pin, while the low side mosfet is connected between the lxb2 pin and gnd. vcore buck output voltage setting the regulated default output voltag e as shown in the following equation : the recommended value for r11 should be up to 10k without some sacrificing. place t he resistor divider as close as possible to the chip can reduce noise sensitivity. the output voltage also can be adjusted from ? 7% to 7% by setting the i 2 c register 04h [3:0]. vcore buck soft-start the synchronous buck converter has an internal soft-start to reduce the input inrush current. when the converter is enabled, the output voltage rises slowly from zero to the regulated voltage. the typical soft-start time is around 300 s. vcore buck over current protection the ic has a cycle-by-cycle low side source current sensing algorithm that uses the on-resistance of the low side mosfet as a current sensing element, so that costly sense resistors are not required. the dhb2 and dlb2 will be turned off if the low side mosfet source current reaches setting value. moreover, ic will restart after 50ms if over current remains 7 cycles. low side source peak current limit threshold is 1/8 voltage at the ilimt2 pin. meanwhile, the real current limit value need consider the on-resistance of the low side mosfet. ?? ?? ?? core fbb2 fbb2 r11 v = v 1 + , where v = 0.8v (typ.) r12 ilimit2 lim_m2 on v i = (a) 8r (switch) when i lim_m2 is ? low side switch current limit ? . vcore buck short circuit protection to limit the short circuit current, the device has a cycle- by-cycle current limit. to avoid the short circuit current from low side mosfet source current limit when the output is shorted to gnd, the switching operation will be stop. the switching operation will stop when the output voltage is below 20%. if the short is removed, the buck converter will resume operation. if the voltage remains below 80% after 50ms, the ic will shut down. vcore buck loop compensation the voltage feedback loop can be compensated with an external compensation network consisted of r23 and c25 and c26. choose r23 to set high frequency integrator gain for fast transient response, c25 and c26 to set the integrator zero to maintain stability.
rt6908 19 ds6908-01 march 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? vcore buck external mosfet selection the v core buck controller drives two external n-mosfets as the switch. there are some considerations to choose the external mosfet. it includes mosfet drain to source voltage stress, on-resistance, total gate charge characteristics and power dissipation for thermal performance. buck inductor selection the inductor value and operating frequency determine the ripple current according to a specific input and output voltage. the ripple current, i l , will increase with higher v in and decrease with higher inductance, as shown in below equation : ??? ? ?? ??? ? ??? ? out out l osc in vv i = 1 fl v having a lower ripple current reduces not only the esr losses in the output capacitors but also the output voltage ripple. high frequency with small ripple current can achieve the highest efficiency operation. however, it requires a large inductor to achieve this goal. for the ripple current selection, the value of i l(max) = 0.4 is a reasonable starting point. the largest ripple current occurs at the highest v in . to guarantee that the ripple current stays below the specified maximum, the inductor value should be chosen according to the following equation : ???? ? ???? ???? out out osc l(max) in(max) vv l = 1 fi v buck input capacitor selection the input capacitance, c in , is needed to filter the trapezoidal current at the source of the high-side mosfet. to prevent large ripple current, a low esr input capacitor sized for the maximum rms current should be used. the rms current is given by : ? out in rms out(max) in out v v i = i 1 vv this formula has a maximum at vin = 2v out , where i rms = i out / 2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. for the input capacitor, a 10 f low esr ceramic capacitor is recommended. buck output capacitor selection the selection of c out is determined by the required esr to minimize voltage ripple. moreover, the amount of bulk capacitance is also a key for c out selection to ensure that the control loop is stable. loop stability can be checked by viewing the load transient response as described in a later section. the output ripple, v out , is determined by : ?? ?? ?? ?? out l osc out 1 v = i esr + 8f c the output ripple will be highest at the maximum input voltage since i l increases with input voltage. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirement. suitable candidates such as dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. special polymer capacitors offer very low esr value. however, it provides lower capacitance density than other types. although tantalum capacitors have the highest capacitance density, it is important to only use types that pass the surge test for use in switching power supplies. aluminum electrolytic capacitors have significantly higher esr. however, it can be used in cost-sensitive applications requiring high ripple current rating and long term reliability. ceramic capacitors have excellent low esr characteristics but can have a high voltage coefficient and audible piezoelectric effects. the high q of ceramic capacitors with trace inductance can also lead to significant ringing. nevertheless, higher value, lower cost ceramic capacitors are now becoming available in smaller case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. however, care must be taken when these capacitors are used at the input and output. when a ceramic capacitor is used at the input, vin, and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input. at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at vin large enough to damage the part.
rt6908 20 ds6908-01 march 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? vgl negative regulator the vgl negative regulator controller provides low level voltage for gate driver. the linear regulator can provide a programmable output voltage. the output voltage can be adjusted by setting the i 2 c register 02h [5:0]. the vgl negative regulator controller has a fault protection. this function can disable the vgl negative regulator controller when the vgl voltage is detected to be above vgl + 2v. if the voltage remains above vgl + 2v after 50ms, the ic will shut down. moreover, if vgl voltage above ? 0.5v, the idrvn source current will be limited to 300 a for short circuit protection. vgh positive regulator the vgh positive regulator controller provides high level voltage for gate driver. the linear regulator can provide a programmable output voltage. the output voltage can be adjusted by setting the i 2 c register 01h [4:0]. the vgh positive regulator controller has a fault protection. this function can disable the vgh regulator controller when the vgh voltage is detected to be below 75%. if the vgh voltage remains below 75% after 50ms, the ic will shut down. moreover, if vgh voltage remains below 20%, the i drvp sink current will be limited to 80 a for short circuit protection. voltage detector the voltage detector monitors the v det voltage to generate the rstb pin signal. the rstb pin will be floating and pulled high by v i/o if v det is higher than the detecting level. moreover, the detector power on delay can be determined by connect capacitor to the crst pin and ground. the detecting level and delay time can be determined as the following equations : det det 9 r25 detect voltage, falling = v 1 + , r26 where v =0.6v (typ.) detector delay time = 0.1563 c17 10 (ms) ?? ?? ?? under voltage lockout protection the uvlo circuit compares the input voltage at the avin pin with the uvlo threshold (8.6v rising, typ.) to ensure that the input voltage is high enough for reliable operation. the 1v (typ.) hysteresis prevents supply transients from causing a shutdown. once the input voltage exceeds the uvlo rising threshold, start-up begins. when the input voltage falls below the uvlo falling threshold, all switch will be turned off and latched. otherwise, input voltage need below 5v (typ.), the ic can be reset. over temperature protection the rt6908 equips an over temperature protection (otp) circuitry to prevent overheating due to excessive power dissipation. the otp will shut down switching operation when junction temperature exceeds 150 c. once the junction temperature cools down by approximately 50 c, the rt6908 will resume operation. to maintain continuous operation maximum, the junction temperature should be prevented from rising above 125 c. thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance. for recommended operating condition specifications of the rt6908, the maximum junction temperature is 125 c and t a is the ambient temperature. the junction to ambient thermal resistance, ja , is layout dependent. for wqfn-40l 5x5 package, the thermal resistance, ja , is 36 c/w on a standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formula : p d(max) = (125 c ? 25 c) / (36 c/w) = 2.778w for wqfn-40l 5x5 package the maximum power dissipation depends on the operating ambient temperature for fixed t j(max) and thermal resistance, ja . for the rt6908 package, the derating
rt6908 21 ds6908-01 march 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? layout consideration for high frequency switching power supplies, the pcb layout is important to get good regulation, high efficiency and stability. the following descriptions are the guidelines for better pcb layout. ` for good regulation, place the power components as close as possible. the traces should be wide and short enough especially for the high current loop. ` the compensation circuit should be kept away from the power loops and be shielded with a ground trace to prevent any noise coupling. ` minimize the size of all lx nodes and keep them wide and shorter. ` the exposed pad of the chip should be connected to a strong ground plane for maximum thermal consideration. figure 5. derating curve for the rt6908 package 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) 1 four-layer pcb figure 6. pcb layout guide agnd r4 c19 l2 c11 c13 r3 v i/o v in l1 pgnd c1 d1 c5 c2 r38 c28 agnd avdd avdd l3 c24 pgnd r23 c25 c26 v core r11 r12 agnd agnd v in v in c12 r2 q1 c20 m1 m2 place the power components as close as possible. the traces should be wide and short especially for the high-current loop. the exposed pad of the chip should be connected to ground plane for thermal consideration. separate power ground (pgnd) and analog ground (agnd). connect the agnd and the pgnd islands at a single end. make sure that there are no other connections between these separate ground planes. the power ground (pgnd) cons ists of input and output capacitor grounds, the components's ground of charge pump. the pgnd should be wi de and short enough to connect to a ground plane. place the power components as close as possible. the compensation circuit should be kept away from the power loops and should be shielded with a ground trace to prevent any noise coupling. place the power components as close as possible. the traces should be wide and short especially for the high current loop. the compensation circuit should be kept away from the power loops and should be shielded with a ground trace to prevent any noise coupling. v in c54 c21 pgnd rstb comp1 lxi gd avdd vdet sda scl fbb1 boot2 nc dhb2 drvn crst comp2 fbb2 dlb2 ilimit2 lxb2 comp a0 pgnd lx lx lx pgnd vgl vgh drvp lxb1 lxb1 boot1 nc vinb1 avin agnd vl en en_i2c 1 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 31 32 33 34 35 36 37 38 39 40 41 pgnd v in curve in figure 5 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation.
rt6908 22 ds6908-01 march 2013 www.richtek.com richtek technology corporation 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 richtek products are sold by description only. richtek reserves the right to change the circuitry and/or specifications without notice at any time. customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a richtek product. information furnish ed by richtek is believed to be accurate and reliable. however, no responsibility is assumed by richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of r ichtek or its subsidiaries. outline dimension dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.150 0.250 0.006 0.010 d 4.950 5.050 0.195 0.199 d2 3.250 3.500 0.128 0.138 e 4.950 5.050 0.195 0.199 e2 3.250 3.500 0.128 0.138 e 0.400 0.016 l 0.350 0.450 0.014 0.018 w-type 40l qfn 5x5 package note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options 1 1 2 2 d e d2 e2 l b a a1 a3 e 1 see detail a

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